Patent · US Active

Latency measurements for wireless communications

US8138790B1 · kind B1 · utility

3Cited by

2References

19Claims

0Family size

Assignee

Lattice Semiconductor Corporation · US

Inventors

James Doubler · Wheaton, US
Michael Hammer · Westchester, US
Jin Zhang · Sichuan, CN

Key dates

Filing date	Apr 11, 2011
Grant date	Mar 20, 2012
Priority date	—
Expiry date	Apr 11, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH04J3/0682
WIPO fieldTelecommunications
WIPO sectorElectrical engineering

Abstract

In one embodiment, a programmable logic device (PLD) includes a programmable fabric and hard logic coupled to the programmable fabric. The hard logic includes a timing measurement circuit adapted to measure latency of a data path between first and second points in the programmable logic device, such as the latency of a data path through a link interface configured within the programmable fabric.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.