High signal level compliant input/output circuits
US8138814B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2008 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Jul 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018507
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a second signal level. Electronic components of the first and second stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter and the second stage level shifter prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.