Front-end architecture of RF transceiver and transceiver chip thereof
US8138853B2 · kind B2 · utility
20Cited by
4References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 22, 2009 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Feb 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/48
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An RF front-end architecture is operated in either a transmitting or a receiving mode. The RF front-end architecture comprises an antenna, an impedance match network, a balun and a transceiver chip. The transceiver chip comprises first and second transmit/receive (TR) switches, a transmitter, and a receiver. Because two TR switches are integrated into the chip, the printed circuit board area, BOM cost and pin count of the transceiver chip can be greatly reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.