Dynamic quadrature clock correction for a phase rotator system
US8139700B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2009 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Sep 10, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.