Phase interpolation-based clock and data recovery for differential quadrature phase shift keying
US8139701B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 5, 2010 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Aug 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0069
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method includes receiving N input streams; generating a recovered clock signal based on the input data bits in the N input streams, the recovered clock signal having a clock frequency and a recovered clock phase; generating a clock signal for each one of the N input streams based on the recovered clock signal having the clock frequency and a respective phase at a respective phase offset relative to the recovered clock phase; detecting a phase difference between each of the N input bit streams and the respective N clock signals; and adjusting the phases of the N clock signals to eliminate the respective phase differences, the adjusting comprising shifting the N respective clock phase offsets such that each of the N clock signals is locked to the input data bits in the respective one of the N input streams.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.