Integrated circuit biasing a microphone
US8139790B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 2008 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Jan 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04R19/016
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The invention provides an integrated circuit. The integrated circuit receives a first signal from a microphone via a first node. In one embodiment, the integrated circuit comprises a biasing circuit and a buffering circuit. The biasing circuit is coupled between the first node and a second node, drives the microphone with a first voltage source, and filters the first signal to generate a second signal at the second node. In one embodiment, the biasing circuit comprises a first resistor, a first capacitor, and a load element. The first resistor is coupled between the first voltage source and the first node. The first capacitor is coupled between the first node and the second node. The load element is coupled between the second node and a second voltage source. The buffering circuit is coupled between the second node and a third node and buffers the second signal to generate a third signal at the third node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.