Transmitter built-in production line testing utilizing digital gain calibration
US8140031B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2007 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Mar 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/13
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A novel and useful self-calibration based production line testing mechanism utilizing built-in closed loop measurements in the radio to calibrate the output power of an external power amplifier coupled to a SoC radio. The mechanism is applicable during production line testing and calibration which is performed on each SoC and associated external power amplifier after assembly at the target PCB of the final product. The mechanism calibrates the TX output power in three phases based on loopback EVM measurements. In a first phase, the PPA in the radio (SoC) is calibrated and gain versus output power is stored in a gain table in on-chip NVS. In a second phase, the maximum PPA TX power is determined using closed loop EVM measurements. The external PA is calibrated in a third phase and the maximum PA power is determined. During this third phase, the maximum power of the device is calculated, compared to the requirements of the particular standard and a pass/fail determination is thereby made.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.