Patent · US Active

Multi-level page-walk apparatus for out-of-order memory controllers supporting virtualization technology

US8140781B2 · kind B2 · utility

3Cited by

0References

17Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Chee Hak Teh · Kampung Bukit Kechil, MY
Arthur Hunter · Cameron Park, US

Key dates

Filing date	Dec 31, 2007
Grant date	Mar 20, 2012
Priority date	—
Expiry date	Dec 21, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The invention relates generally to computer memory access. Embodiments of the invention provide a multi-level page-walk apparatus and method that enable I/O devices to execute multi-level page-walks with an out-of-order memory controller. In embodiments of the invention, the multi-level page-walk apparatus includes a demotion-based priority grant arbiter, a page-walk tracking queue, a page-walk completion queue, and a command packetizer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.