Efficient read/write algorithms and associated mapping for block-level data reduction processes
US8140821B1 · kind B1 · utility
433Cited by
19References
17Claims
0Family size
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Key dates
| Filing date | Dec 18, 2009 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Aug 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2206/1004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system configured to optimize access to stored chunks of data is provided. The system comprises a vLUN layer, a mapped LUN layer, and a mapping layer disposed between the vLUN and the mapped LUN. The vLUN provides a plurality of logical chunk addresses (LCAs) and the mapped LUN provides a plurality of physical chunk addresses (PCAs), where each LCA or PCA stores a respective chunk of data. The mapping layer defines a layout of the mapped LUN that facilitates efficient read and write access to the mapped LUN.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.