Integrated device, layout method thereof, and program
US8140874B2 · kind B2 · utility
1Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2008 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Nov 22, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated device includes at least one data processing device and at least one memory macro accessible by the data processing device. The data processing device and the memory macro are laid out so that a memory address and a power consumption have a correlation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.