Hardware process trace facility
US8140903B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2009 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Jan 1, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/87
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread comprising an ordered series of thread instructions. In the event the first thread instruction is a set bus trace enable bit (BTEB) instruction, the processor sets a bus trace enable bit corresponding to the thread. In the event the BTEB is set, the processor determines whether the first thread instruction is a trace-eligible instruction and, in the event the first thread instruction is a trace-eligible instruction, and the BTEB is set, the processor sets a snoop tag trace enable bit (STTEB). A hardware trace monitor (HTM) monitors bus transactions, each bus transaction comprising a STTE. In the event a monitored bus transaction comprises a set STTEB, the HTM stores the bus transaction as trace data. In the event a monitored bus transaction comprises a reset STTEB, the HTM does not store the bus transaction as trace data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.