Patent · US Active

Semiconductor memory device and error correction method thereof

US8140938B2 · kind B2 · utility

7Cited by

18References

22Claims

0Family size

Assignee

ELPIDA MEMORY, INC. · JP

Inventors

Yutaka Ito · Tokyo, JP
Shigeo Takeuchi · Nagoya, JP

Key dates

Filing date	Apr 23, 2008
Grant date	Mar 20, 2012
Priority date	—
Expiry date	Jun 3, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/1044
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A semiconductor memory device having an error correcting function, includes a memory array having a data area and a check code area, an operation circuit including an encode circuit coupled to the data area and the check code area, and a decode circuit coupled to the check code area, and a control circuit including a first register coupled to the operation circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.