Method and system of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models
US8141013B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2009 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Jun 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models such as distributed transmission line models and on-chip spiral inductor models includes recognizing a passive device such as a distributed transmission line device and an on-chip spiral inductor device, interpreting data obtained from the recognizing the passive device, breaking the passive device into a plurality of sections, the plurality of sections including a terminal of a model call, extracting parameters of the passive device by Layout Versus Schematic (LVS) and parasitic extraction, connecting the terminal to a pre-layout passive network by selectively low and high resistive paths set by the parameters of the passive device depending on whether crossing lines are present or not present in one of the plurality of sections, connecting the terminal to a distributed passive model, and coupling the crossing lines to the terminal via capacitors produced in an extracted netlist with the passive device having distributed coupling to a plurality of crossing lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.