Patent · US Active

Method and apparatus for preventing congestive placement

US8141023B2 · kind B2 · utility

0Cited by

3References

20Claims

0Family size

Assignee

MSTAR SEMICONDUCTOR, INC. · TW

Inventors

Chen-Hsing Lo · 東區, TW
Chien-Pang Lu · 東區, TW

Key dates

Filing date	Jul 13, 2009
Grant date	Mar 20, 2012
Priority date	—
Expiry date	Jun 4, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/327
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A congestive placement preventing apparatus, applied in a logic circuit layout having 2K logic circuits, where K is a positive integer, is provided. The congestive placement preventing apparatus includes a restructuring module and a synthesizing module. The restructuring module adds a selecting unit in the logic circuit layout, and adds (N−K) buffers in each of the 2K logic circuits, where N is a positive integer. The synthesizing module synthesizes the restructured logic circuit layout according to a plurality of “don't touch” synthesizing commands associated with the added buffers. In the synthesized logic circuit layout, all of the 2K logic circuits are independent and not coupled or merged with one another.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.