Method of fabricating extended drain MOS transistor

US8143139B2 · kind B2 · utility

Assignee

• Dongbu HiTek Co., Ltd. · KR

Inventor

• Kyoung Jin LEE · Suwon-si, KR

Key dates

• Filing date: Aug 25, 2008
• Grant date: Mar 27, 2012
• Expiry date: Sep 27, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/116

Abstract

A method of fabricating an extended drain MOS transistor which reduces a design rule and prevents the generation of leakage current. The method includes sequentially forming a diffusion film, a first conductive epitaxial layer, a gate oxide layer and a hard mask layer over a semiconductor substrate, forming a first hard mask pattern having a first thickness by performing a first etching process on the hard mask layer, forming a second hard mask pattern having a second thickness by performing a second etching process on the first hard mask layer, and then forming a thin gate oxide layer by performing a third etching process on the gate oxide layer using the second hard mask pattern as a mask.