Self aligned field effect transistor structure
US8143670B2 · kind B2 · utility
1Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2009 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Dec 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
Provided is a self aligned filed effect transistor structure. The self aligned field effect transistor structure includes: an active region on a substrate; a U-shaped gate insulation pattern on the active region; and a gate electrode self-aligned by the gate insulation pattern and disposed in an inner space of the gate insulation pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.