Multilayer chip varistor
US8143992B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2009 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Jul 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01C7/18
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multilayer chip varistor is provided as one capable of suppressing production of cracks and thereby preventing a connection failure between an internal electrode and a through-hole conductor. An internal electrode 21 is so configured as to be curved toward a direction of penetration of a through hole 10 in a connection portion 28 thereof to a through-hole conductor 27. By this configuration, a region T sandwiched between a curved surface 28a of the connection portion 28 and the through-hole conductor 27 is formed in a varistor layer 9 near the connection portion 28. In this region T, a metal concentration thereof becomes higher because of diffusion of metal of the internal electrode 21 and the through-hole conductor 27 into the varistor layer 9, and therefore, after completion of firing, the region T has an intermediate contraction percentage between that of the internal electrode 21 and through-hole conductor 27 and that of the other region of the varistor layer 9. This permits the region T to relax stress near the connection portion 28 where the internal electrode 21, through-hole conductor 27, and varistor layer 9 are congested so as to readily produce cracks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.