Two-by-two pixel structure in an imaging system-on-chip
US8144226B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2008 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Sep 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/778
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The claimed subject matter provides systems and/or methods that facilitate mitigating an impact resulting from mismatch between signal chains in a CMOS imaging System-on-Chip (iSoC) sensor. Two-by-two pixel structures can be a basic building block upon which a pixel array is constructed. Further, each two-by-two pixel structure can be associated with a read bus that carries a sampled signal to a top end and a bottom end of a chip. Moreover, multiplexers at either end of the chip can select a subset of the read buses from which to receive a subset of the sampled signals. Accordingly, pixels in a first color plane can be read, processed, etc. on the same side of the chip (e.g., utilizing a common signal chain), while pixels in at least one second color plane can be read, processed, etc. on the other side of the chip (e.g., employing a differing signal chain).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.