Static random access memory
US8144502B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 18, 2010 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Sep 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Included are a memory cell, a first metal interconnection, a variable capacitance circuit and a connection switch. The memory cell includes cross-coupled first and second inverters which are connected to a power supply node. The first metal interconnection is connected to the power supply node. The variable capacitance circuit includes: second and third metal interconnections electrically connected to a connection node; and a controller capable of controlling electrical connection between the third metal interconnection and the connection node. The connection switch is connected between the first metal interconnection and the connection node of the variable capacitance circuit. The connection switch is configured to electrically connect the first metal interconnection and the connection node in a write operation of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.