Memory reading method for resistance drift mitigation
US8144508B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2011 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Jan 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In one embodiment of the invention, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.