High throughput fine timing
US8144683B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2007 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Dec 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2695
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
After detecting the predetermined phase rotation, a receiver can advantageously remove any cyclic shifting delays (CSDs) from the mixed mode packet for each chain. Once any CSDs are removed, the receiver can perform timing offset estimation and decode the mixed mode packet. In another embodiment, a timing offset from a channel for a first chain without any CSDs can be estimated. Compensation for the timing offset in the first chain can then be performed. At this point, the CSDs from other chains can then be removed. After CSD removal, compensation for any timing offsets in the other chains can be performed using the timing offset in the first chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.