Clock clean-up phase-locked loop (PLL)
US8145171B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2009 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | May 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/0039
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock clean-up phase-locked loop (PLL) that may reduce spurs and improve performance of a receiver is described. In one exemplary design, an integrated circuit includes a PLL and an analog-to-digital converter (ADC). The PLL receives a first clock signal generated with a fractional divider ratio and having spurs due to abrupt frequency jumps. The first clock signal may be generated by a fractional-N frequency synthesizer external to the integrated circuit. The PLL generates a second clock signal with an integer divider ratio and having reduced spurs. The ADC digitizes an analog baseband signal based on the second clock signal and provides digital samples. The integrated circuit may further include a low noise amplifier (LNA), which may observe less spurs coupled via the substrate of the integrated circuit due to the use of the PLL to clean up the first clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.