Memory controller with write data cache and read data cache

US8145844B2 · kind B2 · utility

Assignee

• Arm Limited · GB

Inventor

• Alistair Crone Bruce · Marple, GB

Key dates

• Filing date: Dec 13, 2007
• Grant date: Mar 27, 2012
• Expiry date: Jun 17, 2029

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/0817
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory controller includes a write data cache, a read data cache and coherency circuitry. The coherency circuitry manages coherency of data between the write data cache, the read data cache and data stored within a main memory when servicing read requests and write requests received by the memory controller. Write complete signals are issued back to a write requesting circuit as soon as a write request has had its write data stored within the write data cache.