Patent · US Active

Fast ECC memory testing by software including ECC check byte

US8145961B2 · kind B2 · utility

4Cited by

11References

10Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Andreas Arnez · Schenefeld, DE
Joerg-Stephan Vogt · Holzgerlingen, DE

Key dates

Filing date	May 19, 2008
Grant date	Mar 27, 2012
Priority date	—
Expiry date	Jan 4, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/42
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.