Error correcting
US8145976B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 2008 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Dec 14, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6505
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one or more embodiments, a method, computer-readable media, and/or computational unit acts or is capable of receiving, from a single, integrated memory, current and previous iterations of Log Likelihood Ratio (“LLR”) parameters for a current iteration of a Low-Density Parity-Check code (“LDPC code”) error-correcting process. These may then perform an LDPC code error-correcting algorithm using the current and previous iterations of LLR parameters. Following this, these embodiment(s) may overwrite the previous iteration of LLR parameters with a now-current iteration of LLR parameters and treat the current iteration of LLR parameters as a now-previous iteration of LLR parameters. Both of these iterations of LLR parameters for the now-current iteration may then be received following overwrite of the previous iteration of LLR parameters with the now-current iteration of LLR parameters. With these now-current and now-previous iterations of LLR parameters these embodiment(s) may perform the LDPC code error-correcting algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.