Low voltage transistors

US8148718B2 · kind B2 · utility

Assignee

• The Regents of the University of California · US

Inventors

• Peter M. Asbeck · San Diego, US
• Lingquan Wang · Irvine, US

Key dates

• Filing date: Jun 2, 2008
• Grant date: Apr 3, 2012
• Expiry date: Jun 2, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/82

Abstract

The invention provides a transistor having a substrate, a structure supported by the substrate including a source, drain, gate, and channel, wherein the source and the channel are made of different materials, and a tunnel junction formed between the source and the channel, whereby the tunnel junction is configured for injecting carriers from the source to the channel.