Low loss package for electronic device
US8148823B1 · kind B1 · utility
1Cited by
11References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2009 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | Sep 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package for one or more semiconductor die is described. A generally rectangular package includes two large terminals that occupy substantially the entire length of the package and provide low resistance connections. Additional connections may be provided preferably in a central portion of a short end of the package. BGA connections between the semiconductor die and the package substrate provide low impedance connections between the die and the package contacts. The package and connections facilitate current flow orthogonal to the longest package dimension maximizing conductor width and minimizing interconnection resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.