Multi-output PLL output shift
US8149035B2 · kind B2 · utility
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9References
8Claims
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Assignee
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Key dates
| Filing date | Feb 2, 2010 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | Feb 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Controlling a PLL includes providing a voltage controlled oscillator (VCO) and coupling an output of the VCO to a shifter circuit. The shifter circuit has a shifter circuit output, the shifter circuit also including an activation input for receiving an activation signal, the shifter circuit causing at least one pulse of the output signal to be suppressed at the shifter output upon receipt of the activation signal. Controlling also includes coupling the shifter circuit output to a first frequency divider.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.