Multi-mode bit rate processor
US8149702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2008 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | Mar 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/1829
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.