Clock/data recovery circuit
US8149978B2 · kind B2 · utility
3Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2007 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | Jul 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0087
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock/data recovery circuit includes a data duty correction circuit which outputs corrected data by correcting the duty of input data in accordance with the level of a correction signal, a clock recovery circuit which generates a recovered clock in synchronism with the edge timing of the corrected data, a data decision circuit which performs data decision of the corrected data based on the recovered clock, and a data duty detection circuit which detects the duty of the corrected data based on the recovered clock and outputs the correction signal representing a duty correction amount to the data duty correction circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.