Reconfigurable virtual backplane systems and methods
US8151024B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2009 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | Jul 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/4625
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Reconfigurable virtual backplane systems and methods are provided. One virtual backplane system includes a bus, and first and second line cards coupled to the bus. Each line card includes a processor including a memory storing an array of configuration tables. Each configuration table stores a listing of processes to be transmitted to or received from the communication bus, wherein a first configuration table is selected from the first line card upon the occurrence of a first event and a second configuration table is selected from the second line card upon the occurrence of a second event. One method includes connecting first and second buses in first and second systems, respectively, to form a bus for a new system. The method further includes detecting the connection of the first and second buses, and reconfiguring the first and second systems to operate as the new system in response to detecting the connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.