Method of increasing DDR memory bandwidth in DDR SDRAM modules
US8151030B2 · kind B2 · utility
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4References
25Claims
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Key dates
| Filing date | May 25, 2005 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | Oct 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of increasing DDR memory bandwidth in DDR SDRAM modules. DDR memory has an inherent feature called the Variable Early Read command, where the read command is issued one CAS latency before the termination of an ongoing data burst By using the Variable Early Read command the effect of the CAS latency is minimized in terms of the effect on bandwidth. The enhanced bandwidth technology achieved with this invention optimizes the remaining two access latencies (tRP and tRCD) for optimal bandwidth. These optimizations in the SPD allow for much better bandwidth in real world applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.