Patent · US Active

Mapping memory segments in a translation lookaside buffer

US8151076B2 · kind B2 · utility

1Cited by

5References

17Claims

0Family size

Assignee

Cisco Technology, Inc. · US

Inventors

Victor Kamensky · Fremont, US
Ilya Umansky · San Jose, US

Key dates

Filing date	Apr 4, 2008
Grant date	Apr 3, 2012
Priority date	—
Expiry date	Apr 1, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/1021
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, a method includes identifying first and second memory segments associated with a process in virtual memory, allocating memory for the first memory segment from a first contiguous physical memory space, allocating memory for the second memory segment from a second contiguous physical memory space, and mapping the first and second memory segments to the first and second contiguous physical memory spaces in a translation lookaside buffer. Apparatus and logic for memory allocation to minimize translation lookaside buffer faults are also disclosed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.