Configuring routing in mesh networks
US8151088B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2008 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | Nov 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions and is configurable to transmit data from an initial processor core or an input/output device to an intermediate processor core based on a first dimension ordering policy, and from the intermediate processor core to a destination processor core. The first dimension ordering policy specifies an ordering of the dimensions of the interconnection network when routing data through the interconnection network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.