Fault tolerant decoding method and apparatus
US8151175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2007 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | May 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/154
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bit quality evaluator receives a sequence of bits. The bit sequence is provided to a decoding device that performs soft decision convolutional decoding on the sequence of bits. An off track event detector detects an occurrence of a trellis decode path change during the convolutional decoding operation and identifies a first symbol proximate corresponding to the occurrence of the trellis decode path change. An erasure decision circuit identifies at least the first symbol for erasure. The output of the first decoder and the erasure decision circuit are received at a second decoder, which decoder decodes the output of the first decoder after erasing at least the first symbol. The erasure decision circuit may also identify additional symbols for erasure using performance measures of the trellis decode path and using quality measures of the sequence of bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.