Semiconductor bond pad patterns and method of formation
US8153510B2 · kind B2 · utility
3Cited by
6References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 26, 2010 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Aug 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor wafer, the polyimide film underneath a power metal structure is partially etched to create corresponding surface depressions of the conformal top power metal. The depressions at the surface of power metal are visible under optical microscopy. Arrangement of the depressions in a pattern facilitates the alignment of probe needles, set-up of automated wire bonding and microscopic inspection for precise alignment of wire bonds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.