Systems and methods for generating equalization data using shift register architecture
US8154815B2 · kind B2 · utility
4Cited by
55References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2008 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Oct 7, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/10046
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present invention provide systems and methods for data equalization. For example, various embodiments of the present invention provide methods for generating equalization data. The method includes inputting N bits of an equalization data pattern into respective stages of a shift register, wherein inputting the N bits occurs synchronous to a system data clock having a system data rate, and shifting the N bits of equalization data to next adjacent next stages of the shift register synchronous to an equalization data clock having an equalization data rate N times the system data rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.