Resistance variable memory apparatus
US8154909B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2011 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Jun 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated with a selected nonvolatile memory element, apply a second voltage V2 to a second wire (BL) associated with the selected nonvolatile memory element, apply a third voltage V3 to a first wire (WL) which is not associated with the selected nonvolatile memory element and apply a fourth voltage V4 to a second wire (BL) which is not associated with the selected memory element when writing data or reading data, wherein V2≦V3<V5 and V5<V4≦V1 are satisfied and (V1−V4)<VF or (V3−V2)<VF is satisfied when V5=(V1+V2)/2 is a fifth voltage V5.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.