Decoding circuit withstanding high voltage via low-voltage MOS transistor and the implementing method thereof
US8154945B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2009 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Mar 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source of a PMOS transistor in the CMOS inverter is switched to high resistance, and the substrate to the ground; the source of an NMOS transistor in the first CMOS inverter is connected with a half negative high voltage, and the source of an NMOS transistor in the second CMOS inverter with a negative high voltage; the first CMOS inverter, whose output is the half negative high voltage, is grounded at its input terminal, and output of the second CMOS inverter is the negative high voltage. The present invention further discloses a method of implementing the decoding circuit and a memory circuit using the decoding circuit. The present invention can effectively reduce area the device occupies; it is applicable to the non-volatile memory field, realizing high-voltage output during a high-voltage operation and fast decoding output during a normal-voltage operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.