Processing data in a parallel processing environment
US8155113B1 · kind B1 · utility
63Cited by
2References
16Claims
0Family size
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Inventor
Key dates
| Filing date | Dec 13, 2005 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Jan 20, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a plurality of tiles, and a plurality of interface modules coupled to the switches of a subset of the tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles. At least some of the interface modules are configured to multiplex data from one or more parallel communication links of the switch to an multiplexed communication link having reduced parallelization, and mediate between a network protocol of the switch and a communication protocol of the multiplexed communication link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.