Asymmetric decision feedback equalization slicing in high speed transceivers
US8155214B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2009 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Aug 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03146
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An asymmetric DFE receiver circuit is disclosed. The receiver circuit includes a voltage measuring unit configured to determine a signal voltage of a received signal, and a comparator unit configured to calculate a difference between the signal voltage and an evaluation threshold voltage and to compare the difference to the value of a midpoint voltage. The comparator unit is configured to generate a first control signal if the difference is greater than the midpoint voltage value or a second control signal if the signal voltage is less than the midpoint voltage value. The receiver includes an adjustment circuit configured to adjust the evaluation threshold voltage toward the signal voltage if the first control signal is generated and away from the signal voltage if the second control signal is generated. The rates of adjustment may vary depending upon whether the received signal is a transition bit or a non-transition bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.