Shift register and gate driver therefor
US8155261B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 9, 2009 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Jun 30, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a shift register and a gate driver therefor. The shift register comprises: a first thin film transistor, of which a gate is connected to a first node, a source is connected to a clock signal terminal, and a drain is connected to an output terminal at current stage; a second thin film transistor, of which a gate is connected to a second node, a source is connected to the output terminal at current stage, and a drain is connected to a low level signal terminal; a third thin film transistor, of which a gate is connected to the first node, a source is connected to the low level signal terminal, and a drain is connected to the second node; a fourth thin film transistor, of which a gate is connected to the second node, a source is connected to the low level signal terminal, and a drain is connected to the first node; a first capacitor connected between the clock signal terminal and the second node; a discharging module connected between the clock signal terminal and the output terminal at current stage; a compensation module connected between the first node and the low level signal terminal. The present invention has the advantages of low cost, low power …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.