Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set
US8156307B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2007 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Aug 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor system comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set. The system further comprises at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor's instruction set to be dynamically reconfigured. In this manner, the at least one host processor and the at least one dynamically reconfigurable co-processor are heterogeneous processors having different instruction sets. Further, cache coherency is maintained between the heterogeneous host and co-processors. And, a single executable file may contain instructions that are processed by the multi-processor system, wherein a portion of the instructions are processed by the host processor and a portion of the instructions are processed by the co-processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.