Overlapping state areas for programmable crypto processing circuits
US8156321B2 · kind B2 · utility
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2References
24Claims
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Assignee
Inventors
Key dates
| Filing date | Feb 5, 2009 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Oct 18, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method for operating a field-programmable logic chip or circuit (FPLC) is disclosed. Operation of the FPLC includes a configuration state and a cryptographic processing state. Switching between states is controlled by a state machine. Each state has one or more images. Transferring between states causes some or all images from the other state being overwritten.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.