Validating data using processor instructions
US8156401B2 · kind B2 · utility
11Cited by
23References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2011 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Feb 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/005
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a method for determining from a data block in a buffer a number of first operands in a first portion of the buffer and a number of second operands in a second portion of the buffer. Based on these numbers, a cyclic redundancy checksum (CRC) operation may be iteratively performed on the first and second operands to obtain a checksum result. The first and second operands are of a different length, and the checksum operation may be executed using processor instructions corresponding to the different lengths. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.