Semiconductor device including insulating layer of cubic system or tetragonal system
US8159012B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2008 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | May 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02189
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.