Semiconductor integrated circuit device having a dummy metal wiring line
US8159013B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2009 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Nov 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.