Recalibration systems and techniques for electronic memory applications
US8159888B2 · kind B2 · utility
5Cited by
2References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2010 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Nov 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a delay module receiving a strobe signal and producing a delayed strobe signal therefrom. The memory circuit also includes a calibration module that initiates recalibration of the delay module when the calibration module discerns that the delayed strobe signal is within a predetermined proximity of an edge of a reference signal. The memory circuit can be included in a memory interface. Furthermore, in some embodiments, a strobe signal can be used as the reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.