Data switch
US8160086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2008 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Aug 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5674
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulated spread spectrum clock (SSC) enabled source having predetermined spread spectrum link clock frequency characteristics, and at least one output for transmitting the data packets after passage through the switch, the switch further comprising at least one receive buffer having a link side and a core side for receiving the SSC modulated input data packets from the link, at least one transmit buffer and a core clock, wherein the core clock operates at a given frequency between predetermined error limits determined by oscillation accuracy alone and is not SSC-enabled, the core clock frequency being set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.