Signal interleaving for serial clock and data recovery
US8160192B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2007 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Jun 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock and data recovery (CDR) system and method for recovering timing information and data from a serial data stream. The CDR system includes a sampling circuit that produces a recovered clock/data signal and an interleaving feedback network that provides feedback to the sampling circuit. The feedback network includes a logic circuit that produces control signals based on the recovered clock/data signal, a first multiplexer that selects from four phases of a global clock signal based on a control signal, a first delay-locked loop having a first set of delay cells coupled to a second multiplexer that produces a delayed signal based on the selected global clock signal, and a second delay-locked loop having a second set of delay cells that produces a set of phase-shifted feedback signals that are applied to the sampling circuit to phase-align the sampling circuit with the transitions in the received serial data stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.